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| CY7C68001 EZ-USB SX2TM High Speed USB Interface Device 1. Features 2. Applications USB 2.0-Certified Compliant On the USB-IF Integrators List: Test ID Number 40000713 Operates at High (480 Mbps) or Full (12 Mbps) Speed Supports Control Endpoint 0: Used for handling USB device requests Supports Four Configurable Endpoints that share a 4-KB FIFO Space Endpoints 2, 4, 6, 8 for application-specific control and data Standard 8- or 16-bit External Master Interface Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs Synchronous or Asynchronous interface Integrated Phase-locked Loop (PLL) 3.3V Operation, 5V Tolerant I/Os 56-pin SSOP and QFN Package Complies with most Device Class Specifications DSL modems ATA interface Memory card readers Legacy conversion devices Cameras Scanners Home PNA Wireless LAN MP3 players Networking Printers The "Reference Designs" section of the Cypress web site, www.cypress.com, provides additional tools for typical USB applications. Each reference design comes complete with firmware source code and object code, schematics, and documentation. 3. Logic Block Diagram SCL I2C Bus Controller (Master Only) WAKEUP* RESET# SDA IFCLK* 24 MHz XTAL PLL Read*, Write*, OE*, PKTEND*, CS# Interrupt#, Ready SX2 Internal Logic Flags (3/4) Address (3) Control VCC 1.5K FIFO Data Bus USB 2.0 XCVR CY Smart USB FS/HS Engine 4 KB FIFO Data 8/16-Bit Data DPLUS DMINUS Cypress Semiconductor Corporation Document #: 38-08013 Rev. *J * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 07, 2009 [+] Feedback CY7C68001 4. Introduction The EZ-USB SX2TM USB interface device is designed to work with any external master, such as standard microprocessors, DSPs, ASICs, and FPGAs to enable USB 2.0 support for any peripheral design. SX2 has a built in USB transceiver and Serial Interface Engine (SIE), along with a command decoder for sending and receiving USB data. The controller has four endpoints that share a 4 KB FIFO space for maximum flexibility and throughput, and Control Endpoint 0. SX2 has three address pins and a selectable 8- or 16- bit data bus for command and data input or output. Figure 4-1. Example USB System Diagram 5.3 Boot Methods During the power up sequence, internal logic of the SX2 checks for the presence of an I2C EEPROM.[1,2] If it finds an EEPROM, it boots off the EEPROM. When the presence of an EEPROM is detected, the SX2 checks the value of first byte. If the first byte is found to be a 0xC4, the SX2 loads the next two bytes into the IFCONFIG and POLAR registers, respectively. If the fourth byte is also 0xC4, the SX2 enumerates using the descriptor in the EEPROM, then signals to the external master when enumeration is complete through an ENUMOK interrupt (See "Interrupt System" on page 3.). If no EEPROM is detected, the SX2 relies on the external master for the descriptors. After this descriptor information is received from the external master, the SX2 connects to the USB and enumerates. 5.3.1 EEPROM Organization W indows/U S B C apable H ost The valid sequence of bytes in the EEPROM are displayed in the following table. Table 5-1. Descriptor Length Set to 0x06: Default Enumeration USB C able Byte Index U S B C onnection Description 0xC4 IFCONFIG POLAR 0xC4 Descriptor Length (LSB):0x06 Descriptor Length (MSB): 0x00 VID (LSB) VID (MSB) PID (LSB) PID (MSB) DID (LSB) DID (MSB) 0 1 2 C ypress S X2 R A M /R O M D evice C P U EEPROM 3 4 5 6 7 8 9 A pplication 5. Functional Overview 5.1 USB Signaling Speed SX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000: 10 11 Table 5-2. Descriptor Length Not Set to 0x06 Byte Index 0 1 2 3 4 5 6 7 8 0xC4 IFCONFIG POLAR 0xC4 Descriptor Length (LSB) Descriptor Length (MSB Descriptor[0] Descriptor[1] Descriptor[2] Description Full speed, with a signaling bit rate of 12 Mbits/s High speed, with a signaling bit rate of 480 Mbits/s. SX2 does not support the low speed signaling rate of 1.5 Mbits/s. 5.2 Buses SX2 features: A selectable 8- or 16-bit bidirectional data bus An address bus for selecting the FIFO or Command Interface. Notes 1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0 to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-byte EEPROMs (24LC64, etc.) should be strapped to address 001. 2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull up values are 2.2K-10K Ohms. Document #: 38-08013 Rev. *J Page 2 of 45 [+] Feedback CY7C68001 IFCONFIG: The IFCONFIG byte contains the settings for the IFCONFIG register. The IFCONFIG register bits are defined in IFCONFIG Register 0x01 on page 17. If the external master requires an interface configuration different from the default, that interface can be specified by this byte. POLAR: The Polar byte contains the polarity of the FIFO flag pin signals. The POLAR register bits are defined in POLAR Register 0x04 on page 18. If the external master requires signal polarity different from the default, the polarity can be specified by this byte. Descriptor: The Descriptor byte determines if the SX2 loads the descriptor from the EEPROM. If this byte = 0xC4, the SX2 loads the descriptor starting with the next byte. If this byte does not equal 0xC4, the SX2 waits for descriptor information from the external master. Descriptor Length: The Descriptor length is within the next two bytes and indicate the length of the descriptor contained within the EEPROM. The length is loaded least significant byte (LSB) first, then most significant byte (MSB). Byte Index 6 Starts Descriptor Information: The descriptor can be a maximum of 500 bytes. Endpoint 2: Bulk out, 512 bytes in high speed mode, 64 bytes in full speed mode Endpoint 4: Bulk out, 512 bytes in high speed mode, 64 bytes in full speed mode Endpoint 6: Bulk in, 512 bytes in high speed mode, 64 bytes in full speed mode Endpoint 8: Bulk in, 512 bytes in high speed mode, 64 bytes in full speed mode. The entire default descriptor is listed in Default Descriptor on page 37 of this data sheet. 5.4 Interrupt System 5.4.1 Architecture The SX2 provides an output signal that indicates to the external master that the SX2 has an interrupt condition, or that the data from a register read request is available. The SX2 has six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK, BUSACTIVITY, and READY. Each interrupt can be enabled or disabled by setting or clearing the corresponding bit in the INTENABLE register. When an interrupt occurs, the INT# pin is asserted, and the corresponding bit is set in the Interrupt Status Byte. The external master reads the Interrupt Status Byte by strobing SLRD/SLOE. This presents the Interrupt Status Byte on the lower portion of the data bus (FD[7:0]). Reading the Interrupt Status Byte automatically clears the interrupt. Only one interrupt request occurs at a time; the SX2 buffers multiple pending interrupts. If the external master has initiated a register read request, the SX2 buffers interrupts until the external master has read the data. This insures that after a read sequence has begun, the next interrupt that is received from the SX2 indicates that the corresponding data is available. Following is a description of this INTENABLE register. 5.4.2 INTENABLE Register Bit Definition Bit 7: SETUP If this interrupt is enabled, and the SX2 receives a setup packet from the USB host, the SX2 asserts the INT# pin and sets bit 7 in the Interrupt Status Byte. This interrupt only occurs if the setup request is not one that the SX2 automatically handles. For complete details on how to handle the SETUP interrupt, refer to Endpoint 0 on page 8 of this data sheet. 5.3.2 Default Enumeration An optional default descriptor can be used to simplify enumeration. Only the Vendor ID (VID), Product ID (PID), and Device ID (DID) need to be loaded by the SX2 for it to enumerate with this default setup. This information is either loaded from an EEPROM in the case when the presence of an EEPROM (Table 5-1) is detected, or the external master may simply load a VID, PID, and DID when no EEPROM is present. In this default enumeration, the SX2 uses the in-built default descriptor (refer to Default Descriptor on page 37). If the descriptor length loaded from the EEPROM is 6, SX2 loads a VID, PID, and DID from the EEPROM and enumerate. The VID, PID, and DID are loaded LSB, then MSB. For example, if the VID, PID, and DID are 0x0547, 0x1002, and 0x0001, respectively, then the bytes should be stored as: 0x47, 0x05, 0x02, 0x10, 0x01, 0x00. If there is no EEPROM, SX2 waits for the external master to provide the descriptor information. To use the default descriptor, the external master must write to the appropriate register (0x30) with descriptor length equal to 6 followed by the VID, PID, and DID. Refer to Default Enumeration on page 8 for further information on how the external master may load the values. The default descriptor enumerates the following endpoints: Document #: 38-08013 Rev. *J Page 3 of 45 [+] Feedback CY7C68001 Bit 6: EP0BUF If this interrupt is enabled, and the Endpoint 0 buffer becomes available to the external master for read or write operations, the SX2 asserts the INT# pin and sets bit 6 in the Interrupt Status Byte. This interrupt is used for handling the data phase of a setup request. For complete details on how to handle the EP0BUF interrupt, refer to Endpoint 0 on page 8 of this data sheet. Bit 5: FLAGS If this interrupt is enabled, and any OUT endpoint FIFO's state changes from empty to not empty and from not empty to empty, the SX2 asserts the INT# pin and sets bit 5 in the Interrupt Status Byte. This is an alternate way to monitor the status of OUT endpoint FIFOs instead of using the FLAGA-FLAGD pins, and can be used to indicate when an OUT packet has been received from the host. Bit 2: ENUMOK If this interrupt is enabled and the SX2 receives a SET_CONFIGURATION request from the USB host, the SX2 asserts the INT# pin and sets bit 2 in the Interrupt Status Byte. This event signals the completion of the SX2 enumeration process. Bit 1: BUSACTIVITY If this interrupt is enabled, and the SX2 detects either an absence or resumption of activity on the USB bus, the SX2 asserts the INT# pin and sets bit 1 in the Interrupt Status Byte. This usually indicates that the USB host is either suspending or resuming or that a self-powered device has been plugged in or unplugged. If the SX2 is bus-powered, the external master must put the SX2 into a low power mode after detecting a USB suspend condition to be USB-compliant. Bit 0: READY If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set when the SX2 has powered up and performed a self-test. The external master should always wait for this interrupt before trying to read or write to the SX2, unless an external EEPROM with a valid descriptor is present. If an external EEPROM with a valid descriptor is present, the ENUMOK interrupt occurs instead of the READY interrupt after power up. A READY interrupt also occurs if the SX2 is awakened from a low power mode via the WAKEUP pin. This READY interrupt indicates that the SX2 is ready for commands or data. 5.4.3 Qualify with READY Pin on Register Reads It is true that all interrupts are buffered after a command read request has been initiated. However, in very rare conditions, there might be a situation when there is a pending interrupt already, when a read request is initiated by the external master. In this case it is the interrupt status byte that is output when the external master asserts the SLRD. So, a condition exists where the Interrupt Status Data Byte can be mistaken for the result of a command register read request. In order to get around this possible race condition, the first thing that the external master must do on getting an interrupt from the SX2 is check the status of the READY pin. If the READY is low at the time the INT# was asserted, the data that is output when the external master strobes the SLRD is the interrupt status byte (not the actual data requested). If the READY pin is high at the time when the interrupt is asserted, the data output on strobing the SLRD is the actual data byte requested by the external master. So it is important that the state of the READY pin be checked at the time the INT# is asserted to ascertain the cause of the interrupt. 5.5 Resets and Wakeup 5.5.1 Reset An input pin (RESET#) resets the chip. The internal PLL stabilizes after VCC has reached 3.3V. Typically, an external RC network (R = 100 KOhms, C = 0.1 F) is used to provide the RESET# signal. The Clock must be in a stable state for at least 200 s before the RESET is released. 5.5.2 USB Reset When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it like any other enumeration sequence. This means that SX2 enumerates again and assert the ENUMOK interrupt to let the external master know that it has enumerated. The external master is then responsible for configuring the SX2 for the application. The external master should also check whether SX2 enumerated at High or Full speed in order to adjust the EPxPKTLENH/L register values accordingly. The last initialization task is for the external master to flush all of the SX2 FIFOs. 5.5.3 Wakeup The SX2 exits its low power state when one of the following events occur: USB bus signals a resume. The SX2 asserts a BUSACTIVITY interrupt. The external master asserts the WAKEUP pin. The SX2 asserts a READY interrupt[3]. 5.6 Endpoint RAM 5.6.1 Size Control endpoint: 64 Bytes: 1 x 64 bytes (Endpoint 0). FIFO Endpoints: 4096 Bytes: 8 x 512 bytes (Endpoint 2, 4, 6, 8). Organization EP0-Bidirectional Endpoint 0, 64-byte buffer. EP2, 4, 6, 8-Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and EP6 can be either double-, triple-, or quad-buffered. EP4 and EP8 can only be double-buffered. For high speed endpoint configuration options, see Figure 8-1. on page 11. Note 3. If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic performs RESUME signalling after a WAKEUP interrupt. Document #: 38-08013 Rev. *J Page 4 of 45 [+] Feedback CY7C68001 Figure 5-1. Endpoint Configurations (High Speed Mode) E P 0 IN & O U T 64 64 64 64 64 64 G ro u p A 512 512 1024 512 512 G ro u p C 512 1024 1024 EP2 EP2 512 512 EP2 1024 EP2 512 512 EP4 512 512 EP2 512 1024 1024 G ro u p B 512 512 1024 512 512 512 EP2 EP6 512 1024 1024 EP6 EP6 512 512 EP6 512 1024 512 EP8 512 512 EP8 512 EP8 512 1024 Endpoint 0 is the same for every configuration as it serves as the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to Figure 8-1. on page 11. Endpoints 2, 4, 6, and 8 may be configured by choosing either: 5.7.1 Architecture The SX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (IFCLK, CS#, SLRD, SLWR, SLOE, PKTEND, and FIFOADR[2:0]). The SX2 command interface is used to set up the SX2, read status, load descriptors, and access Endpoint 0. The command interface has its own READY signal for gating writes, and an INT# signal to indicate that the SX2 has data to be read, or that an interrupt event has occurred. The command interface uses the same control signals (IFCLK, CS#, SLRD, SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface, except for PKTEND. 5.7.2 Control Signals FIFOADDR Lines The SX2 has three address pins that are used to select either the FIFOs or the command interface. The addresses correspond to the following table. Table 5-3. FIFO Address Lines Setting Address/Selection FIFO2 FIFO4 FIFO6 FIFO8 COMMAND RESERVED RESERVED RESERVED FIFOADR2 FIFOADR1 FIFOADR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 One configuration from Group A and one from Group B One configuration from Group C. EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-buffered. EP2: 512 bytes double-buffered, EP4: 512 bytes double-buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes double buffered. EP2: 1024 bytes quad-buffered. Some example endpoint configurations are as follows. 5.6.2 Default Endpoint Memory Configuration At power-on-reset, the endpoint memories are configured as follows: EP2: Bulk OUT, 512 bytes/packet, 2x buffered. EP4: Bulk OUT, 512 bytes/packet, 2x buffered. EP6: Bulk IN, 512 bytes/packet, 2x buffered. EP8: Bulk IN, 512 bytes/packet, 2x buffered. 5.7 External Interface The SX2 presents two interfaces to the external master. 1. A FIFO interface through which EP2, 4, 6, and 8 data flows. 2. A command interface, which is used to set up the SX2, read status, load descriptors, and access Endpoint 0. Document #: 38-08013 Rev. *J Page 5 of 45 [+] Feedback CY7C68001 The SX2 accepts either an internally derived clock (30 MHz or 48 MHz) or externally supplied clock (IFCLK, 5 to 50 MHz), and SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals from an external master. The interface can be selected for 8- or 16- bit operation by an internal configuration bit, and an Output Enable signal SLOE enables the data bus driver of the selected width. The external master must ensure that the output enable signal is inactive when writing data to the SX2. The interface can operate either asynchronously where the SLRD and SLWR signals act directly as strobes, or synchronously where the SLRD and SLWR act as clock qualifiers. The optional CS# signal tristates the data bus and ignore SLRD, SLWR, PKTEND. The external master reads from OUT endpoints and writes to IN endpoints, and reads from or writes to the command interface. Read: SLOE and SLRD In synchronous mode, the FIFO pointer is incremented on each rising edge of IFCLK while SLRD is asserted. In asynchronous mode, the FIFO pointer is incremented on each asserted-to-deasserted transition of SLRD. SLOE is a data bus driver enable. When SLOE is asserted, the data bus is driven by the SX2. Write: SLWR In synchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of IFCLK while SLWR is asserted. In asynchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each asserted-to-deasserted transition of SLWR. PKTEND PKTEND commits the current buffer to USB. To send a short IN packet (one which has not been filled to max packet size determined by the value of PL[X:0] in EPxPKTLENH/L), the external master strobes the PKTEND pin. All these interface signals have a default polarity of low. In order to change the polarity of PKTEND pin, the master may write to the POLAR register anytime. In order to switch the polarity of the SLWR/SLRD/SLOE, the master must set the appropriate bits 2, 3 and 4 respectively in the FIFOPINPOLAR register located at XDATA space 0xE609. Please note that the SX2 powers up with the polarities set to low. POLAR Register 0x04 on page 18 provides further information on how to access this register located at XDATA space. 5.7.3 IFCLK The IFCLK pin can be configured to be either an input (default) or an output interface clock. Bits IFCONFIG[7:4] define the behavior of the interface clock. To use the SX2's internally-derived 30- or 48 MHz clock, set IFCONFIG.7 to 1 and set IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). To use an externally supplied clock, set IFCONFIG.7=0 and drive the IFCLK pin (5 MHz to 50 MHz). The input or output IFCLK signal can be inverted by setting IFCONFIG.4=1. 5.7.4 FIFO Access An external master can access the slave FIFOs either asynchronously or synchronously: Asynchronous-SLRD, SLWR, and PKTEND pins are strobes. Synchronous-SLRD, SLWR, and PKTEND pins are enables for the IFCLK clock pin. An external master accesses the FIFOs through the data bus, FD [15:0]. This bus can be either 8- or 16-bits wide; the width is selected via the WORDWIDE bit in the EPxPKTLENH/L registers. The data bus is bidirectional, with its output drivers controlled by the SLOE pin. The FIFOADR[2:0] pins select which of the four FIFOs is connected to the FD [15:0] bus, or if the command interface is selected. 5.7.5 FIFO Flag Pins Configuration The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD. These FLAGx pins report the status of the FIFO selected by the FIFOADR[2:0] pins. At reset, these pins are configured to report the status of the following: FLAGA reports the status of the programmable flag. FLAGB reports the status of the full flag. FLAGC reports the status of the empty flag. FLAGD defaults to the CS# function. The FIFO flags can either be indexed or fixed. Fixed flags report the status of a particular FIFO regardless of the value on the FIFOADR [2:0] pins. Indexed flags report the status of the FIFO selected by the FIFOADR [2:0]pins.[4] 5.7.6 Default FIFO Programmable Flag Setup By default, FLAGA is the Programmable Flag (PF) for the endpoint being pointed to by the FIFOADR[2:0] pins. For EP2 and EP4, the default endpoint configuration is BULK, OUT, 512, 2x; the PF pin asserts when the entire FIFO has 512 bytes. For EP6 and EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts when the entire FIFO has less than/equal to 512 bytes. In other words, EP6/8 report a half-empty state, and EP2/4 report a half-full state. 5.7.7 FIFO Programmable Flag (PF) Setup Each FIFO's programmable-level flag (PF) asserts when the FIFO reaches a user-defined fullness threshold. That threshold is configured as follows: 1. For OUT packets: The threshold is stored in PFC12:0. The PF is asserted when the number of bytes in the entire FIFO is less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold. 2. For IN packets, with PKTSTAT = 1: The threshold is stored in PFC9:0. The PF is asserted when the number of bytes written into the current packet in the FIFO is less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold. 3. For IN packets, with PKTSTAT = 0: The threshold is stored in two parts: PKTS2:0 holds the number of committed packets, and PFC9:0 holds the number of bytes in the current packet. The PF is asserted when the FIFO is at or less full than (DECIS = 0), or at or more full than (DECIS = 1), the threshold. Note 4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}). Document #: 38-08013 Rev. *J Page 6 of 45 [+] Feedback CY7C68001 5.7.8 Command Protocol An address of [1 0 0] on FIFOADR [2:0] selects the command interface. The command interface is used to write to and read from the SX2 registers and the Endpoint 0 buffer, as well as the descriptor RAM. Command read and write transactions occur over FD[7:0] only. Each byte written to the SX2 is either an address or a data byte, as determined by bit7. If bit7 = 1, then the byte is considered an address byte. If bit7 = 0, then the byte is considered a data byte. If bit7 = 1, then bit6 determines whether the address byte is a read request or a write request. If bit6 = 1, then the byte is considered a read request. If bit6 = 0 then the byte is considered a write request. Bits [5:0] hold the register address of the request. The format of the command address byte is shown in Table 5-4. Table 5-4. Command Address Byte Address/ Data# Read/ Write# A5 A4 A3 A2 A1 A0 The first bit signifies an address transfer. The second bit signifies that this is a write command. The next six bits represent the register address (000001 binary = 0x01 hex). After the byte has been received the SX2 pulls the READY pin low to inform the external master not to send any more information. When the SX2 is ready to receive the next byte, the SX2 pulls the READY pin high again. This next byte, the upper nibble of the data byte, is written to the SX2 as follows. Table 5-8. Command Data Write Byte One Address/Da ta# 0 Don't Care X Don't Care X Don't Care X D7 1 D6 0 D5 1 D4 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The first bit signifies that this is a data transfer. The next three are don't care bits. The next four bits hold the upper nibble of the transferred byte. Each Write request is followed by two or more data bytes. If another address byte is received before both data bytes are received, the SX2 ignores the first address and any incomplete data transfers. The format for the data bytes is shown in Table 5-5 and Table 5-6. Some registers take a series of bytes. Each byte is transferred using the same protocol. Table 5-5. Command Data Byte One Bit 7 0 Bit 6 X Bit 5 X Bit 4 X Bit 3 D7 Bit 2 D6 Bit 1 D5 Bit 0 D4 After the byte has been received the SX2 pulls the READY pin low to inform the external master not to send any more information. When the SX2 is ready to receive the next byte, the SX2 pulls the READY pin high again. This next byte, the lower nibble of the data byte is written to the SX2. Table 5-9. Command Data Write Byte Two Address/ Data# 0 Don't Care X Don't Care X Don't Care X D3 0 D2 0 D1 0 D0 0 Table 5-6. Command Data Byte Two Bit 7 0 Bit 6 X Bit 5 X Bit 4 X Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 At this point the entire byte <10110000> is transferred to register 0x01 and the write sequence is complete. Read Request Example The Read cycle is simpler than the write cycle. The Read cycle consists of a read request from the external master to the SX2. For example, to read the contents of register 0x01, a command address byte is written to the SX2 as follows. Table 5-10. Command Address Read Byte Address/Da ta# 1 Read/ Write# 1 A5 0 A4 0 A3 0 A2 0 A1 0 A0 1 The first command data byte contains the upper nibble of data, and the second command byte contains the lower nibble of data. Write Request Example Prior to writing to a register, two conditions must be met: FIFOADR[2:0] must hold [1 0 0], and the Ready line must be HIGH. The external master should not initiate a command if the READY pin is not in a HIgh state. Example: to write the byte <10110000> into the IFCONFIG register (0x01), first send a command address byte as follows. Table 5-7. Command Address Write Byte Address/Da ta# 1 Read/ Write# 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 1 When the data is ready to be read, the SX2 asserts the INT# pin to tell the external master that the data it requested is waiting on FD[7:0].[5] Note 5. An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources described in Interrupt System on page 3 is asserted, the SX2 buffers that interrupt until the read request completes. Document #: 38-08013 Rev. *J Page 7 of 45 [+] Feedback CY7C68001 6. Enumeration The SX2 has two modes of enumeration. The first mode is automatic through EEPROM boot load, as described in Boot Methods on page 2. The second method is a manual load of the descriptor or VID, PID, and DID as described in the following section. 6.2 Default Enumeration The external master may simply load a VID, PID, and DID and use the default descriptor built into the SX2. To use the default descriptor, the descriptor length described in the previous section must equal 6. After the external master has written the length, the VID, PID, and DID must be written LSB, then MSB. For example, if the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001 respectively, then the external master does the following: 6.1 Standard Enumeration The SX2 has 500 bytes of descriptor RAM into which the external master may write its descriptor. The descriptor RAM is accessed through register 0x30. To load a descriptor, the external master does the following: Initiates a Write Request to register 0x30. Writes two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred. In this case, the length is always six. Writes the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10, 0x01, 0x00 (in nibble format per the command protocol). Initiate a Write Request to register 0x30. Write two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred. The LSB is written first, followed by the MSB.[6] Write the descriptor, one byte at a time until complete.[6] Note: the register address is only written once. The default descriptor is listed in Default Descriptor on page 37. The default descriptor can be used as a starting point for a custom descriptor. 7. Endpoint 0 The SX2 automatically responds to USB chapter 9 requests without any external master intervention. If the SX2 receives a request to which it cannot respond automatically, the SX2 notifies the external master. The external master then has the choice of responding to the request or stalling. After the SX2 receives a setup packet to which it cannot respond automatically, the SX2 asserts a SETUP interrupt. After the external master reads the Interrupt Status Byte to determine that the interrupt source was the SETUP interrupt, it can initiate a read request to the SETUP register, 0x32. When the SX2 sees a read request for the SETUP register, it presents the first byte of setup data to the external master. Each additional read request presents the next byte of setup data, until all eight bytes have been read. The external master can stall this request at this or any other time. To stall a request, the external master initiates a write request for the SETUP register, 0x32, and writes any non-zero value to the register. If this setup request has a data phase, the SX2 then interrupts the external master with an EP0BUF interrupt when the buffer becomes available. The SX2 determines the direction of the setup request and interrupts when either: IN: the Endpoint 0 buffer becomes available to write to, or OUT: the Endpoint 0 buffer receives a packet from the USB host. For an IN setup transaction, the external master can write up to 64 bytes at a time for the data phase. The steps to write a packet are as follows: 1. Wait for an EP0BUF interrupt, indicating that the buffer is available. 2. Initiate a write request for register 0x31. 3. Write one data byte. 4. Repeat steps 2 and 3 until either all the data or 64 bytes have been written, whichever is less. 5. Write the number of bytes in this packet to the byte count register, 0x33. After the entire descriptor has been transferred, the SX2 floats the pull up resistor connected to D+, and parse through the descriptor to locate the individual descriptors. After the SX2 has parsed the entire descriptor, the SX2 connects the pull up resistor and enumerate automatically. When enumeration is complete, the SX2 notifies the external master with an ENUMOK interrupt. The format and order of the descriptor should be as follows (see Default Descriptor on page 37 for an example): Device. Device qualifier. High speed configuration, high speed interface, high speed endpoints. Full speed configuration, full speed interface, full speed endpoints. String. The SX2 can be set to run in full speed only mode. To force full speed only enumeration write a 0x02 to the unindexed register CT1 at address 0xE6FB before downloading the descriptors. This disables the chirp mechanism forcing the SX2 to come up in full speed only mode after the descriptors are loaded. The CT1 register can be accessed using the unindexed register mechanism. Examples of writing to unindexed registers are shown in Resetting Data Toggle on page 9. Each write consists of a command write with the target register followed by the write of the upper nibble of the value followed by the write of the lower nibble of the value. Note 6. These and all other data bytes must conform to the command protocol. Document #: 38-08013 Rev. *J Page 8 of 45 [+] Feedback CY7C68001 To send more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified in the wLength field (bytes 6,7) of the setup packet. To send less than the requested amount of data, the external master writes a packet that is less than 64 bytes, or if a multiple of 64, the external master follows the data with a zero-length packet. When the SX2 sees a short or zero-length packet, it completes the setup transfer by automatically completing the handshake phase. The SX2 does not enable more data than the wLength field specified in the setup packet. Note: the PKTEND pin does not apply to Endpoint 0. The only way to send a short or zero length packet is by writing to the byte count register with the appropriate value. For an OUT setup transaction, the external master can read each packet received from the USB host during the data phase. The steps to read a packet are as follows: 1. Wait for an EP0BUF interrupt, indicating that a packet was received from the USB host into the buffer. 2. Initiate a read request for the byte count register, 0x33. This indicates the amount of data received from the host. 3. Initiate a read request for register 0x31. 4. Read one byte. 5. Repeat steps 3 and 4 until the number of bytes specified in the byte count register has been read. To receive more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified in the wLength field of the setup packet (bytes 6,7). When the SX2 sees that the specified number of bytes have been received, it completes the set up transfer by automatically completing the handshake phase. If the external master does not wish to receive the entire transfer, it can stall the transfer. If the SX2 receives another setup packet before the current transfer has completed, it interrupts the external master with another SETUP interrupt. If the SX2 receives a setup packet with no data phase, the external master can accept the packet and complete the handshake phase by writing zero to the byte count register. The SX2 automatically responds to all USB standard requests covered in chapter 9 of the USB 2.0 specification except the Set/Clear Feature Endpoint requests. When the host issues a Set Feature or a Clear feature request, the SX2 triggers a SETUP interrupt to the external master. The USB spec requires that the device respond to the Set endpoint feature request by doing the following: The USB spec requires that the device respond to the Clear endpoint feature request by doing the following: Reset the Data Toggle for that endpoint Clear the STALL condition of that endpoint. The register that is used to reset the data toggle TOGCTL (located at XDATA location 0xE683) is not an index register that can be addressed by the command protocol presented in Command Protocol on page 7. The following section provides further information on this register bits and how to reset the data toggle accordingly using a different set of command protocol sequence. 7.1 Resetting Data Toggle Table 7-1. Bit definition of the TOGCTL register TOGCTL Bit # Bit Name Read/Write Default 7 Q R 0 6 S W 0 5 R W 1 4 I/O R/W 1 3 EP3 R/W 0 2 EP2 R/W 0 1 EP1 R/W 1 0xE683 0 EP0 R/W 0 Bit 7: Q, Data Toggle Value Q=0 indicates DATA0 and Q=1 indicates DATA1, for the endpoint selected by the I/O and EP3:0 bits. Write the endpoint select bits (IO and EP3:0), before reading this value. Bit 6: S, Set Data Toggle to DATA1 After selecting the desired endpoint by writing the endpoint select bits (IO and EP3:0), set S=1 to set the data toggle to DATA1. The endpoint selection bits should not be changed while this bit is written. Bit 5: R, Set Data Toggle to DATA0 Set R=1 to set the data toggle to DATA0. The endpoint selection bits should not be changed while this bit is written. Bit 4: IO, Select IN or OUT Endpoint Set this bit to select an endpoint direction prior to setting its R or S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN endpoint. Bit 3-0: EP3:0, Select Endpoint Set these bits to select an endpoint prior to setting its R or S bit. Valid values are 0, 1, 2, 6, and 8. Set the STALL condition on that endpoint. Document #: 38-08013 Rev. *J Page 9 of 45 [+] Feedback CY7C68001 A two-step process is employed to clear an endpoint data toggle bit to 0. First, write to the TOGCTL register with an endpoint address (EP3:EP0) plus a direction bit (IO). Keeping the endpoint and direction bits the same, write a "1" to the R (reset) bit. For example, to clear the data toggle for EP6 configured as an "IN" endpoint, write the following values sequentially to TOGCTL: 00010110b 00110110b Following is the sequence of events that the master should perform to set this register to 0x16: Send the actual value to write to the register Register (in this case 0x16) Command address write of address0x3C Command data write of upper nibble of the register value (0x01) Command data write of lower nibble of the register value (0x06) The same command sequence needs to be followed to set TOGCTL register to 0x36. The same command protocol sequence can be used to reset the data toggle for the other endpoints. In order to read the status of this register, the external master must do the following sequence of events: Send Low Byte of the Register (0x83) Command address write of address 0x3A Command data write of upper nibble of the Low Byte of Register Address (0x08) Command data write of lower nibble of the Low Byte of Register Address (0x03) Send High Byte of the Register (0xE6) Command address write of address 0x3B Command data write of upper nibble of the High Byte of Register Address (0x0E) Command data write of lower nibble of the High Byte of Register Address (0x06) Send Low Byte of the Register (0x83) Command address write of 0x3A Command data write of upper nibble of the Low Byte of Register Address (0x08) Command data write of lower nibble of the Low Byte of Register Address (0x03) Send High Byte of the Register (0xE6) Command address write of address 0x3B Command data write of upper nibble of the High Byte of Register Address (0x0E) Command data write of lower nibble of the High Byte of Register Address (0x06) Get the actual value from the TOGCTL register (0x16) Command address READ of 0x3C Document #: 38-08013 Rev. *J Page 10 of 45 [+] Feedback CY7C68001 8. Pin Configurations Figure 8-1. CY7C68001 56-Pin SSOP Pin Assignment[7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FD13 FD14 FD15 GND NC VCC GND *SLRD *SLWR AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND *IFCLK RESERVED SCL SDA VCC FD0 FD1 FD2 FD3 FD12 FD11 FD10 FD9 FD8 *WAKEUP VCC RESET# GND *FLAGD/CS# *PKTEND FIFOADR1 FIFOADR0 FIFOADR2 *SLOE INT# READY VCC *FLAGC *FLAGB *FLAGA GND VCC GND FD7 FD6 FD5 FD4 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Note 7. A * denotes programmable polarity. Document #: 38-08013 Rev. *J Page 11 of 45 [+] Feedback CY7C68001 Figure 8-2. CY7C68001 56-pin QFN Assignment[7] *W AKEUP FD15 FD14 FD13 FD12 FD11 FD10 GND 56 GND VCC 55 VCC FD9 FD8 NC 54 53 52 51 50 49 48 47 46 45 44 43 *SLRD *SLW R AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 RESET# GND *FLAGD/CS# *PKTEND FIFOADR1 FIFOADR0 FIFOADR2 CY7C68001 56-pin QFN 36 35 34 33 32 31 30 29 *SLOE INT# READY VCC *FLAGC *FLAGB *FLAGA *IFCLK RESERVED 15 SCL 16 SDA 17 VCC 18 FD0 19 FD1 20 FD2 21 FD3 22 FD4 23 FD5 24 FD6 25 FD7 26 GND 27 VCC 28 GND Document #: 38-08013 Rev. *J Page 12 of 45 [+] Feedback CY7C68001 8.1 CY7C68001 Pin Definitions Table 8-1. SX2 Pin Definitions QFN SSOP Pin Pin 3 6 9 8 42 5 10 13 16 15 49 12 Name AVCC AGND DMINUS DPLUS RESET# XTALIN Type Power Power I/O/Z I/O/Z Input Input Default N/A N/A Z Z N/A N/A Description Analog VCC. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. USB D- Signal. Connect to the USB D- signal. USB D+ Signal. Connect to the USB D+ signal. Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC through a 100K resistor, and to GND through a 0.1-F capacitor. Crystal Input. Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and 20 pF capacitor to GND. It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source. Crystal Output. Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and 20 pF capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. No Connect. This pin must be left unconnected. READY is an output-only ready that gates external command reads and writes. Active High. INT# is an output-only external interrupt signal. Active Low. SLOE is an input-only output enable with programmable polarity (POLAR.4) for the slave FIFOs connected to FD[7:0] or FD[15:0]. FIFOADR2 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. PKTEND is an input-only packet end with programmable polarity (POLAR.5) for the slave FIFOs connected to FD[7:0] or FD[15:0]. FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master chip select (default). FD[0] is the bidirectional FIFO/Command data bus. FD[1] is the bidirectional FIFO/Command data bus. FD[2] is the bidirectional FIFO/Command data bus. FD[3] is the bidirectional FIFO/Command data bus. FD[4] is the bidirectional FIFO/Command data bus. FD[5] is the bidirectional FIFO/Command data bus. FD[6] is the bidirectional FIFO/Command data bus. FD[7] is the bidirectional FIFO/Command data bus. FD[8] is the bidirectional FIFO data bus. FD[9] is the bidirectional FIFO data bus. FD[10] is the bidirectional FIFO data bus. FD[11] is the bidirectional FIFO data bus. FD[12] is the bidirectional FIFO data bus. FD[13] is the bidirectional FIFO data bus. FD[14] is the bidirectional FIFO data bus. 4 11 XTALOUT Output N/A 54 33 34 35 36 37 38 39 40 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 5 40 41 42 43 44 45 46 47 25 26 27 28 29 30 31 32 52 53 54 55 56 1 2 NC READY INT# SLOE FIFOADR2 FIFOADR0 FIFOADR1 PKTEND Output Output Output Input Input Input Input Input O L H I I I I I I I I I I I I I I I I I I I I I FLAGD/C CS#:I S# FLAGD:O FD[0] FD[1] FD[2] FD[3] FD[4] FD[5] FD[6] FD[7] FD[8] FD[9] FD[10] FD[11] FD[12] FD[13] FD[14] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Document #: 38-08013 Rev. *J Page 13 of 45 [+] Feedback CY7C68001 Table 8-1. SX2 Pin Definitions (continued) QFN SSOP Pin Pin 52 1 2 29 30 31 13 3 8 9 36 37 38 20 Name FD[15] SLRD SLWR FLAGA FLAGB FLAGC IFCLK Type I/O/Z Input Input Output Output Output I/O/Z Default I N/A N/A H H H Z Description FD[15] is the bidirectional FIFO data bus. SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0]. SLWR is the input-only write strobe with programmable polarity (POLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0]. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins. Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals. When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity. Reserved. Must be connected to ground. USB Wakeup. If the SX2 is in suspend, asserting this pin starts up the oscillator and interrupts the SX2 to allow it to exit the suspend mode. During normal operation, holding WAKEUP asserted inhibits the SX2 chip from suspending. This pin has programmable polarity (POLAR.7). I2C Clock. Connect to VCC with a 2.2K-10 KOhms resistor, even if no I2C EEPROM is attached. I2C Data. Connect to VCC with a 2.2K-10 KOhms resistor, even if no I2C EEPROM is attached. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. 14 44 21 51 Reserved WAKEUP Input Input N/A N/A 15 16 22 23 SCL SDA OD OD Z Z 55 7 11 17 27 32 43 53 56 10 12 26 28 41 6 14 18 24 34 39 50 4 7 17 19 33 35 48 VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Document #: 38-08013 Rev. *J Page 14 of 45 [+] Feedback CY7C68001 9. Register Summary Table 9-1. SX2 Register Summary Hex Size 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Name Description General Configuration IFCONFIG Interface Configuration FLAGSAB FIFO FLAGA and FLAGB Assignments FLAGSCD FIFO FLAGC and FLAGD Assignments POLAR FIFO polarities REVID Chip Revision Endpoint Configuration[9] EP2CFG Endpoint 2 Configuration EP4CFG Endpoint 4 Configuration EP6CFG Endpoint 6 Configuration EP8CFG Endpoint 8 Configuration EP2PKTLEN Endpoint 2 Packet Length H H EP2PKTLENL Endpoint 2 Packet Length L (IN only) EP4PKTLEN Endpoint 4 Packet Length H H EP4PKTLENL Endpoint 4 Packet Length L (IN only) EP6PKTLEN Endpoint 6 Packet Length H H EP6PKTLENL Endpoint 6 Packet Length L (IN only) EP8PKTLEN Endpoint 8 Packet Length H H EP8PKTLENL Endpoint 8 Packet Length L (IN only) EP2PFH EP2 Programmable Flag H D7 D6 D5 D4 D3 D2 D1 D0 Default Access IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC STANDBY FLAGD/CS# DISCON 11001001 bbbbbbbb FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 bbbbbbbb FLAGD3 FLAGD2 FLAGD1 WUPOL Major VALID VALID VALID VALID INFM1 PL7 INFM1 PL7 INFM1 PL7 INFM1 PL7 DECIS 0 Major dir dir dir dir OEP1 PL6 OEP1 PL6 OEP1 PL6 OEP1 PL6 PKTSTAT PKTEND Major FLAGD0 SLOE Major FLAGC3 SLRD minor SIZE 0 SIZE 0 0 PL3 0 PL3 0 PL3 0 PL3 IN: PKTS[0] OUT:PFC 10 PFC3 IN: PKTS[0] OUT:PFC 9 PFC3 IN: PKTS[0] OUT:PFC 10 PFC3 IN: PKTS[0] OUT:PFC 9 PFC3 0 0 0 0 0 0 EP3 0 FC3 0 FA3 FLAGC2 SLWR minor STALL STALL STALL STALL PL10 PL2 0 PL2 PL10 PL2 0 PL2 0 FLAGC1 EF minor BUF1 0 BUF1 0 PL9 PL1 PL9 PL1 PL9 PL1 PL9 PL1 PFC9 FLAGC0 00000000 bbbbbbbb FF minor BUF0 0 BUF0 0 PL8 PL0 PL8 PL0 PL8 PL0 PL8 PL0 PFC8 00000000 bbbrrrbb xxxxxxxx rrrrrrrr 10100010 10100000 11100010 11100000 00110010 bbbbbbbb bbbbrbrr bbbbbbbb bbbbrbrr bbbbbbbb TYPE1 TYPE0 TYPE1 TYPE0 TYPE1 TYPE0 TYPE1 TYPE0 ZEROLEN WORDWI DE PL5 PL4 ZEROLEN WORDWI DE PL5 PL4 ZEROLEN WORDWI DE PL5 PL4 ZEROLEN WORDWI DE PL5 PL4 00000000 bbbbbbbb 00110010 bbbbbbbb 00000000 bbbbbbbb 00110010 bbbbbbbb 00000000 bbbbbbbb 00110010 bbbbbbbb 00000000 bbbbbbbb 10001000 bbbbbbbb 13 14 1 1 EP2PFL EP4PFH EP2 Programmable Flag L EP4 Programmable Flag H PFC7 DECIS 15 16 1 1 EP4PFL EP6PFH EP4 Programmable Flag L EP6 Programmable Flag H PFC7 DECIS 17 18 1 1 EP6PFL EP8PFH EP6 Programmable Flag L EP8 Programmable Flag H PFC7 DECIS 19 1A 1B 1C 1D 1E 1F 20 2A 2B 2C 2D 1 1 1 1 1 1 1 1 1 1 1 1 EP8PFL EP8 Programmable Flag L EP2ISOINPK EP2 (if ISO) IN Packets per TS frame (1-3) EP4ISOINPK EP4 (if ISO) IN Packets per TS frame (1-3) EP6ISOINPK EP6 (if ISO) IN Packets per TS frame (1-3) EP8ISOINPK EP8 (if ISO) IN Packets per TS frame (1-3) FLAGS EP24FLAGS Endpoints 2,4 FIFO Flags EP68FLAGS Endpoints 6,8 FIFO Flags INPKTEND/FLUSH[10] INPKTEND/F Force Packet End / Flush LUSH FIFOs USB Configuration USBFRAMEH USB Frame count H USBFRAMEL USB Frame count L MICROFRAM Microframe count, 0-7 E FNADDR USB Function address Interrupts PFC7 0 0 0 0 0 0 FIFO8 0 FC7 0 HSGRANT IN: IN: PKTS[2] PKTS[1] OUT:PFC OUT:PFC1 12 1 PFC6 PFC5 PFC4 PKTSTAT 0 IN: PKTS[1] OUT:PFC1 0 PFC6 PFC5 PFC4 PKTSTAT IN: IN: PKTS[2] PKTS[1] OUT:PFC OUT:PFC1 12 1 PFC6 PFC5 PFC4 PKTSTAT 0 IN: PKTS[1] OUT:PFC1 0 PFC6 PFC5 PFC4 0 0 0 0 0 0 EP4PF EP8PF FIFO6 0 FC6 0 FA6 0 0 0 EP4EF EP8EF FIFO4 0 FC5 0 FA5 0 0 0 EP4FF EP8FF FIFO2 0 FC4 0 FA4 PFC2 0 PFC1 0 PFC0 PFC8 00000000 bbbbbbbb 10001000 bbbbbbbb PFC2 0 PFC1 PFC9 PFC0 PFC8 00000000 bbbbbbbb 00001000 bbbbbbbb PFC2 0 PFC1 0 PFC0 PFC8 00000000 bbbbbbbb 00001000 bbbbbbbb PFC2 0 0 0 0 EP2PF EP6PF EP2 FC10 FC2 MF2 FA2 PFC1 INPPF1 INPPF1 INPPF1 INPPF1 EP2EF EP6EF EP1 FC9 FC1 MF1 FA1 PFC0 00000000 bbbbbbbb INPPF0 00000001 bbbbbbbb INPPF0 00000001 bbbbbbbb INPPF0 00000001 bbbbbbbb INPPF0 00000001 bbbbbbbb EP2FF EP6FF EP0 FC8 FC0 MF0 FA0 00100010 01100110 rrrrrrrr rrrrrrrr 00000000 wwwwww ww xxxxxxxx xxxxxxxx xxxxxxxx 00000000 rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr Document #: 38-08013 Rev. *J Page 15 of 45 [+] Feedback CY7C68001 Table 9-1. SX2 Register Summary (continued) Hex Size Name Description 2E 1 INTENABLE Interrupt Enable 30 31 32 33 3A 3B Descriptor 500 DESC 64 8/1 1 1 1 Descriptor RAM D7 SETUP d7 d7 d7 d7 a7 a7 d7 0 Q D6 EP0BUF d6 d6 d6 d6 a6 a6 d6 0 S D5 FLAGS d5 d5 d5 d5 a5 a5 d5 PKTEND R D4 1 d4 d4 d4 d4 a4 a4 d4 SLOE IO D3 1 d3 d3 d3 d3 a3 a3 d3 SLRD EP3 D2 ENUMOK d2 d2 d2 d2 a2 a2 d2 SLWR EP2 D1 BUSACTIVITY d1 d1 d1 d1 a1 a1 d1 EF EP1 D0 READY d0 d0 d0 d0 a0 a0 d0 FF EP0 00000000 rrbbbbbb xxxxxxxx rbbbbbbb Default Access 11111111 bbbbbbbb xxxxxxxx wwwwww ww xxxxxxxx bbbbbbbb xxxxxxxx bbbbbbbb xxxxxxxx bbbbbbbb 3C 1 Address 0xE609 0xE683 8. Endpoint 0 EP0BUF Endpoint 0 Buffer SETUP Endpoint 0 Setup Data / Stall EP0BC Endpoint 0 Byte Count Un-Indexed Register control Un-Indexed Register Low Byte pointer Un-Indexed Register High Byte pointer Un-Indexed Register Data Un-Indexed Registers in XDATA Space FIFOPINFIFO Interface Pins Polarity POLAR TOGCTL Data Toggle Control Notes 9. Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to change endpoint configurations after the device has already enumerated with a specific configuration, please expect some delay in being able to access the FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 s measured from the time the READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of endpoint configuration registers. 10. Please note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change endpoint configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, please expect some delay in being able to access the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 s measured from the time the READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of endpoint configuration registers. Document #: 38-08013 Rev. *J Page 16 of 45 [+] Feedback CY7C68001 9.1 IFCONFIG Register 0x01 IFCONFIG Bit # Bit Name Read/Write Default 7 IFCLKSRC R/W 1 6 3048 MHZ R/W 1 5 IFCLKOE R/W 0 4 IFCLKPOL R/W 0 3 ASYNC R/W 1 2 STANDBY R/W 0 1 FLAGD/CS# R/W 0 0 DISCON R/W 1 0x01 9.1.1 Bit 7: IFCLKSRC This bit selects the clock source for the FIFOs. If IFCLKSRC = 0, the external clock on the IFCLK pin is selected. If IFCLKSRC = 1 (default), an internal 30 or 48 MHz clock is used. 9.1.2 Bit 6: 3048 MHZ This bit selects the internal FIFO clock frequency. If 3048 MHZ = 0, the internal clock frequency is 30 MHz. If 3048 MHZ = 1 (default), the internal clock frequency is 48 MHz. 9.1.3 Bit 5: IFCLKOE This bit selects if the IFCLK pin is driven. If IFCLKOE = 0 (default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK pin is driven. 9.1.4 Bit 4: IFCLKPOL This bit controls the polarity of the IFCLK signal. or externally on the IFCLK pin, and the FIFO control signals function as read and write enable signals for the clock signal. When ASYNC = 1 (default), the FIFOs operate asynchronously. No clock signal input to IFCLK is required, and the FIFO control signals function directly as read and write strobes. 9.1.6 Bit 2: STANDBY This bit instructs the SX2 to enter a low power mode. When STANDBY=1, the SX2 enters a low power mode by turning off its oscillator. The external master should write this bit after it receives a bus activity interrupt (indicating that the host has signaled a USB suspend condition). If SX2 is disconnected from the USB bus, the external master can write this bit at any time to save power. Once suspended, the SX2 is awakened either by resumption of USB bus activity or by assertion of its WAKEUP pin. 9.1.7 Bit 1: FLAGD/CS# This bit controls the function of the FLAGD/CS# pin. When FLAGD/CS# = 0 (default), the pin operates as a slave chip select. If FLAGD/CS# = 1, the pin operates as FLAGD. 9.1.8 Bit 0: DISCON This bit controls whether the internal pull up resistor connected to D+ is pulled high or floating. When DISCON = 1 (default), the pull up resistor is floating simulating a USB unplug. When DISCON=0, the pull up resistor is pulled high signaling a USB connection. When IFCLKPOL=0, the clock has the polarity shown in all the timing diagrams in this data sheet (rising edge is the activating edge). When IFCLKPOL=1, the clock is inverted (in some cases may help with satisfying data setup times). 9.1.5 Bit 3: ASYNC This bit controls whether the FIFO interface is synchronous or asynchronous. When ASYNC = 0, the FIFOs operate synchronously. In synchronous mode, a clock is supplied either internally 9.2 FLAGSAB/FLAGSCD Registers 0x02/0x03 The SX2 has four FIFO flags output pins: FLAGA, FLAGB, FLAGC, FLAGD. FLAGSAB Bit # Bit Name Read/Write Default FLAGSCD Bit # Bit Name Read/Write Default 7 FLAGD3 R/W 0 6 FLAGD2 R/W 0 5 FLAGD1 R/W 0 4 FLAGD0 R/W 0 3 FLAGC3 R/W 0 2 FLAGC2 R/W 0 1 FLAGC1 R/W 0 0 FLAGC0 R/W 0 7 FLAGB3 R/W 0 6 FLAGB2 R/W 0 5 FLAGB1 R/W 0 4 FLAGB0 R/W 0 3 FLAGA3 R/W 0 2 FLAGA2 R/W 0 1 FLAGA1 R/W 0 0 FLAGA0 R/W 0 0x03 0x02 Document #: 38-08013 Rev. *J Page 17 of 45 [+] Feedback CY7C68001 . These flags can be programmed to represent various FIFO flags using four select bits for each FIFO. The 4-bit coding for all four flags is the same, as shown in Table 9-2. Table 9-2. FIFO Flag 4-bit Coding FLAGx3 FLAGx2 FLAGx1 FLAGx0 0 0 0 0 Pin Function FLAGA = PF, FLAGB = FF, FLAGC = EF, FLAGD = CS# (actual FIFO is selected by FIFOADR[2:0] pins) Reserved Reserved Reserved EP2 PF EP4 PF EP6 PF EP8 PF EP2 EF EP4 EF EP6 EF EP8 EF EP2 FF EP4 FF EP6 FF EP8 FF 9.3.1 Bit 7: WUPOL This flag sets the polarity of the WAKEUP pin. If WUPOL = 0 (default), the polarity is active LOW. If WUPOL=1, the polarity is active HIGH. 9.3.2 Bit 5: PKTEND This flag selects the polarity of the PKTEND pin. If PKTEND = 0 (default), the polarity is active LOW. If PKTEND = 1, the polarity is active HIGH. 9.3.3 Bit 4: SLOE This flag selects the polarity of the SLOE pin. If SLOE = 0 (default), the polarity is active LOW. If SLOE = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load. 9.3.4 Bit 3: SLRD This flag selects the polarity of the SLRD pin. If SLRD = 0 (default), the polarity is active LOW. If SLRD = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load. 9.3.5 SLWR Bit 2 This flag selects the polarity of the SLWR pin. If SLWR = 0 (default), the polarity is active LOW. If SLWR = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load. 9.3.6 EF Bit 1 This flag selects the polarity of the EF pin (FLAGA/B/C/D). If EF = 0 (default), the EF pin is pulled low when the FIFO is empty. If EF = 1, the EF pin is pulled HIGH when the FIFO is empty. 9.3.7 FF Bit 0 This flag selects the polarity of the FF pin (FLAGA/B/C/D). If FF = 0 (default), the FF pin is pulled low when the FIFO is full. If FF = 1, the FF pin is pulled HIGH when the FIFO is full. Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ only bits and cannot be set by the external master or the EEPROM. On power up, these bits are set to active low polarity. In order to change the polarity after the device is powered-up, the external master must access the previously undocumented (un-indexed) SX2 register located at XDATA space at 0xE609. This register has exact same bit definition as the POLAR register except that bits 2, 3 and 4 defined as SLWR, SLRD and SLOE respectively are Read/Write bits. Following is the sequence of events that the master should perform for setting this register to 0x1C (setting bits 4, 3, and 2): 1. Send Low Byte of the Register (0x09) a. Command address write of address 0x3A b. Command data write of upper nibble of the Low Byte of Register Address (0x00) c. Command data write of lower nibble of the Low Byte of Register Address (0x09) 2. Send High Byte of the Register (0xE6) d. Command address write of address 0x3B e. Command data write of upper nibble of the High Byte of Register Address (0x0E) f. Command data write of lower nibble of the High Byte of Register Address (0x06) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 For the default (0000) selection, the four FIFO flags are fixed-function as shown in the first table entry; the input pins FIFOADR[2:0] select to which of the four FIFOs the flags correspond. These pins are decoded as shown in Table 5-3. The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD to correspond to any flag-Programmable, Full, or Empty-from any of the four endpoint FIFOs. This allows each flag to be assigned to any of the four FIFOs, including those not currently selected by the FIFOADR [2:0] pins. For example, the external master could be filling the EP2IN FIFO with data while also checking the empty flag for the EP4OUT FIFO. 9.3 POLAR Register 0x04 This register controls the polarities of FIFO pin signals and the WAKEUP pin. POLAR Bit # Bit Name Read/ Write Default 7 WUPOL R/W 0 6 0 R/W 0 5 4 3 2 1 EF R/W 0 0x04 0 FF R/W 0 PKTEND SLOE R/W 0 R 0 SLRD SLWR R 0 R 0 Document #: 38-08013 Rev. *J Page 18 of 45 [+] Feedback CY7C68001 3. Send the actual value to write to the register Register (in this case 0x1C) g. Command address write of address 0x3C h. Command data write of upper nibble of the register value (0x01) i. Command data write of lower nibble of the register value (0x0C) In order to avoid altering any other bits of the FIFOPINPOLAR register (0xE609) inadvertently, the external master must do a read (from POLAR register), modify the value to set/clear appropriate bits and write the modified value to FIFOPINPOLAR register. The external master may read from the POLAR register using the command read protocol as stated in Command Protocol on page 7. Modify the value with the appropriate bit set to change the polarity as needed and write this modified value to the FIFOPINPOLAR register. 9.5.1 Bit 7: VALID The external master sets VALID = 1 to activate an endpoint, and VALID = 0 to deactivate it. All SX2 endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. (Note: when setting VALID=0, use default values for all other bits.) 9.5.2 Bit 6: DIR 0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for EP6/8 are DIR = 1, IN. 9.5.3 Bit [5,4]: TYPE1, TYPE0 These bits define the endpoint type, as shown in Table 9-3. The TYPE bits apply to all of the endpoint configuration registers. All SX2 endpoints except EP0 default to BULK. Table 9-3. Endpoint Type TYPE1 0 0 1 1 9.5.4 Bit 3: SIZE 0 = 512 bytes (default), 1 = 1024 bytes. Endpoints 4 and 8 can only be 512 bytes and is a read only bit. The size of endpoints 2 and 6 is selectable. 9.5.5 Bit 2: STALL Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the external master sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The Get Status-Endpoint Request returns the STALL state for the endpoint indicated in byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4) specifies direction. 9.5.6 Bit [1,0]: BUF1, BUF0 For EP2 and EP6 the depth of endpoint buffering is selected via BUF1:0, as shown in Table 9-4. For EP4 and EP8 the buffer is internally set to double buffered and are read only bits. Table 9-4. Endpoint Buffering BUF1 0 0 1 1 BUF0 0 1 0 1 Buffering Quad Invalid[11] Double Triple TYPE0 0 1 0 1 Endpoint Type Invalid Isochronous Bulk (Default) Interrupt 9.4 REVID Register 0x05 These register bits define the silicon revision. REVID Bit # Bit Name Read/ Write Default 7 Major R/W X 6 Major R/W X 5 Major R/W X 4 Major R/W X 3 Minor R/W X 2 Minor R/W X 1 Minor R/W X 0x05 0 Minor R/W X The upper nibble is the major revision. The lower nibble is the minor revision. For example: if REVID = 0x11, then the silicon revision is 1.1. 9.5 EPxCFG Register 0x06-0x09 These registers configure the large, data-handling SX2 endpoints, EP2, 4, 6, and 8. Figure 8-1. on page 11 shows the configuration choices for these endpoints. Shaded blocks group endpoint buffers for double-, triple-, or quad-buffering. The endpoint direction is set independently--any shaded block can have any direction. EPxCFG Bit # Bit Name Read/ Write Default . 0x06, 0x08 7 VALID R/W 1 6 DIR R/W 0 5 4 3 SIZE R/W 0 2 STALL R/W 0 1 BUF1 R/W 1 0 BUF0 R/W 0 TYPE1 TYPE0 R/W 1 R/W 0 Note 11. Setting the endpoint buffering to invalid causes improper buffer allocation Document #: 38-08013 Rev. *J Page 19 of 45 [+] Feedback CY7C68001 9.6 EPxPKTLENH/L Registers 0x0A-0x11 The external master can use these registers to set smaller packet sizes than the physical buffer size (refer to the previously described EPxCFG registers). The default packet size is 512 bytes for all endpoints. Note that EP2 and EP6 can have maximum sizes of 1024 bytes, and EP4 and EP8 can have maximum sizes of 512 bytes, to be consistent with the endpoint structure. In addition, the EPxPKTLENH register has four other endpoint configuration bits. EPxPKTLENL Bit # Bit Name Read/Write Default EP2PKTLE NH, EP6PKTLE NH Bit # Bit Name Read/Write Default EP4PKTLEN H, EP8PKTLEN H Bit # Bit Name Read/Write Default 7 6 5 4 3 0 R/W 0 2 0 R/W 0 INFM1 OEP1 ZERO WORD LEN WIDE R/W 0 R/W 0 R/W 1 R/W 1 7 6 5 4 3 0 R/W 0 2 PL10 R/W 0 INFM1 OEP1 ZERO WORD LEN WIDE R/W 0 R/W 0 R/W 1 R/W 1 7 PL7 R/W 0 6 PL6 R/W 0 5 PL5 R/W 0 4 PL4 R/W 0 3 PL3 R/W 0 2 PL2 R/W 0 0x0B, 0x0D, 0x0F, 0x11 1 PL1 R/W 0 0 PL0 R/W 0 0x0A, 0x0E 9.6.3 Bit 5: ZEROLEN EPxPKTLENH.5 When ZEROLEN = 1 (default), a zero length packet is sent when the PKTEND pin is asserted and there are no bytes in the current packet. If ZEROLEN = 0, then a zero length packet is not sent under these conditions. 9.6.4 Bit 4: WORDWIDE EPxPKTLENH.4 This bit controls whether the data interface is 8 or 16 bits wide. If WORDWIDE = 0, the data interface is eight bits wide, and FD[15:8] have no function. If WORDWIDE = 1 (default), the data interface is 16 bits wide. 9.6.5 Bit [2..0]: PL[X:0] Packet Length Bits The default packet size is 512 bytes for all endpoints. 9.7 EPxPFH/L Registers 0x12-0x19 The Programmable Flag registers control when the PF goes active for each of the four endpoint FIFOs: EP2, EP4, EP6, and EP8. The EPxPFH/L fields are interpreted differently for the high speed operation and full speed operation and for OUT and IN endpoints. Following is the register bit definition for high speed operation and for full speed operation (when endpoint is configured as an isochronous endpoint). Full Speed ISO and High Speed Mode: EP2PFL, EP4PFL, EP6PFL, EP8PFL Bit # 7 PFC7 R/W 0 6 PFC6 R/W 0 5 PFC5 R/W 0 4 PFC4 R/W 0 3 PFC3 R/W 0 2 PFC2 R/W 0 Bit Name Read/Write Default 0x13, 0x15, 0x17, 0x19 1 PFC1 R/W 0 0 PFC0 R/W 0 1 PL9 R/W 1 0 PL8 R/W 0 0x0C, 0x10 1 PL9 R/W 1 0 PL8 R/W 0 9.6.1 Bit 7: INFM1 EPxPKTLENH.7 When the external master sets INFM = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid one sample earlier than when the full condition occurs. These bits take effect only when the FIFOs are operating synchronously according to an internally or externally supplied clock. Having the FIFO flag indications one sample early simplifies some synchronous interfaces. This applies only to IN endpoints. Default is INFM1 = 0. 9.6.2 Bit 6: OEP1 EPxPKTLENH.6 When the external master sets an OEP = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid one sample earlier than when the empty condition occurs. These bits take effect only when the FIFOs are operating synchronously according to an internally or externally supplied clock. Having the FIFO flag indications one sample early simplifies some synchronous interfaces. This applies only to OUT endpoints. Default is OEP1 = 0. Full Speed ISO and High Speed Mode: EP4PFH, EP8PFH Bit # 7 6 5 0 4 3 2 0 DECIS PKTSTAT Bit Name Read/Write Default R/W 0 R/W 0 R/W 0 IN: IN: PKTS[1] PKTS[0] OUT: OUT: PFC10 PFC9 R/W 0 R/W 1 0x14, 0x18 1 0 0 PFC8 R/W R/W R/W 0 0 0 Full Speed ISO and High Speed Mode: EP2PFH, EP6PFH Bit # 7 6 5 4 3 2 0 DECIS PKTSTAT Bit Name Read/Write Default R/W 1 R/W 0 IN: IN: IN: PKTS[2] PKTS[1] PKTS[0] OUT: OUT: OUT: PFC12 PFC11 PFC10 R/W 0 R/W 0 R/W 1 0x12, 0x16 1 0 PFC9 PFC8 R/W R/W R/W 0 0 0 Document #: 38-08013 Rev. *J Page 20 of 45 [+] Feedback CY7C68001 Following is the bit definition for the same register when the device is operating at full speed and the endpoint is not configured as isochronous endpoint. Full Speed Non-ISO Mode: EP2PFL, EP4PFL, EP6PFL, EP8PFL Bit # 7 6 5 4 3 2 0x13, 0x15, 0x17, 0x19 1 0 9.7.3 IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3] These three bits have a different meaning, depending on whether this is an IN or OUT endpoint. IN Endpoints If IN endpoint, the meaning of this EPxPFH[5:3] bits depend on the PKTSTAT bit setting. When PKTSTAT = 0 (default), the PF considers when there are PKTS packets plus PFC bytes in the FIFO. PKTS[2:0] determines how many packets are considered, according to Table 9-5. Table 9-5. PKTS Bits PKTS2 PKTS1 0 0 1 1 0 PKTS0 0 1 0 1 0 Number of Packets 0 1 2 3 4 0 0 0 0 1 Bit Name Read/Write Default IN: IN: PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PKTS[1] PKTS[0] OUT: OUT: PFC7 PFC6 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0x12, 0x16 5 4 3 2 0 1 PFC9 0 IN: PKTS[2] OUT: PFC8 R/W 0 0x14, 0x18 6 PKTSTAT R/W 0 5 0 R/W 0 4 3 2 0 1 0 0 PFC8 R/W 0 Full Speed Non-ISO Mode: EP2PFH, EP6PFH Bit # 7 6 DECIS PKTSTAT OUT: OUT: OUT: PFC12 PFC11 PFC10 Bit Name Read/Write Default R/W 1 R/W 0 R/W 0 R/W 0 R/W 1 R/W R/W 0 0 Full Speed Non-ISO Mode: EP4PFH, EP8PFH Bit # Bit Name Read/Write Default 7 DECIS R/W 0 When PKTSTAT = 1, the PF considers when there are PFC bytes in the FIFO, no matter how many packets are in the FIFO. The PKTS[2:0] bits are ignored. OUT Endpoints The PF considers when there are PFC bytes in the FIFO regardless of the PKTSTAT bit setting. OUT: OUT: PFC10 PFC9 R/W 0 R/W 1 R/W R/W 0 0 9.8 EPxISOINPKTS Registers 0x1A-0x1D EP2ISOINOKTS, EP4ISOINPKTS, EP6ISOINPKTS, EP8ISOINPKTS Bit # Bit Name Read/Write Default 7 0 R/W 0 6 0 R/W 0 5 0 R/W 0 4 0 R/W 0 3 0 R/W 0 2 R/W 0 1 R/W 0 0x1A, 0x1B, 0x1C, 0x1D 0 R/W 1 INPPF2 INPPF1 INPPF0 9.7.1 DECIS: EPxPFH.7 If DECIS = 0, then PF goes high when the byte count i is equal to or less than what is defined in the PF registers. If DECIS = 1 (default), then PF goes high when the byte count equal to or greater than what is set in the PF register. For OUT endpoints, the byte count is the total number of bytes in the FIFO that are available to the external master. For IN endpoints, the byte count is determined by the PKSTAT bit. 9.7.2 PKSTAT: EPxPFH.6 For IN endpoints, the PF can apply to either the entire FIFO, comprising multiple packets, or only to the current packet being filled. If PKTSTAT = 0 (default), the PF refers to the entire IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the number of bytes in the current packet. PKTSTAT 0 1 PF applies to EPnPFH:L format Number of committed packets PKTS[] and PFC[] + current packet bytes Current packet bytes only PFC[ ] For ISOCHRONOUS IN endpoints only, these registers determine the number of packets per frame (only one per frame for full speed mode) or microframe (up to three per microframe for high speed mode), according to the following table. Table 9-6. EPxISOINPKTS INPPF1 0 0 1 1 INPPF0 0 1 0 1 Packets Invalid 1 (default) 2 3 Document #: 38-08013 Rev. *J Page 21 of 45 [+] Feedback CY7C68001 9.9 EPxxFLAGS Registers 0x1E-0x1F The EPxxFLAGS provide an alternate way of checking the status of the endpoint FIFO flags. If enabled, the SX2 can interrupt the external master when a flag is asserted, and the external master can read these two registers to determine the state of the FIFO flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and EPxFF bits are actually empty +1 and full -1. EP24FLAGS Bit # Bit Name Read/Write Default EP68FLAGS Bit # Bit Name Read/Write Default 7 0 R/W 0 6 5 4 3 0 R/W 0 2 1 7 0 R/W 0 6 5 4 3 0 R/W 0 2 1 0x1E 0 9.11 USBFRAMEH/L Registers 0x2A, 0x2B Every millisecond, the USB host sends an SOF token indicating "Start Of Frame," along with an 11-bit incrementing frame count. The SX2 copies the frame count into these registers at every SOF. USBFRAMEH Bit # Bit Name Read/Write Default USBFRAMEL Bit # 0x1F 0 Bit Name Read/Write Default 7 FC7 R X 6 FC6 R X 5 FC5 R X 4 FC4 R X 3 FC3 R X 2 FC2 R X 1 FC1 R X 7 0 R X 6 0 R X 5 0 R X 4 0 R X 3 0 R X 2 FC10 R X 1 FC9 R X 0x2A 0 FC8 R x 0x2B 0 FC0 R X EP4PF EP4EF EP4FF R/W 0 R/W 1 R/W 0 EP2PF EP2EF EP2FF R/W 0 R/W 1 R/W 0 EP8PF EP8EF EP8FF R/W 0 R/W 1 R/W 0 EP6PF EP6EF EP6FF R/W 0 R/W 1 R/W 0 9.9.1 EPxPF Bit 6, Bit 2 This bit is the current state of endpoint x's programmable flag. 9.9.2 EPxEF Bit 5, Bit 1 This bit is the current state of endpoint x's empty flag. EPxEF = 1 if the endpoint is empty. 9.9.3 EPxFF Bit 4, Bit 0 This bit is the current state of endpoint x's full flag. EPxFF = 1 if the endpoint is full. One use of the frame count is to respond to the USB SYNC_FRAME Request. If the SX2 detects a missing or garbled SOF, the SX2 generates an internal SOF and increments USBFRAMEL-USBRAMEH. 9.12 MICROFRAME Registers 0x2C MICROFRAME Bit # Bit Name Read/Write Default 7 0 R X 6 0 R X 5 0 R X 4 0 R X 3 0 R X 2 MF2 R X 1 MF1 R X 0x2C 0 MF0 R x 9.10 INPKTEND/FLUSH Register 0x20 This register allows the external master to duplicate the function of the PKTEND pin. The register also allows the external master to selectively flush endpoint FIFO buffers. INPKTEND/FLUSH Bit # Bit Name Read/Write Default 7 6 5 4 3 EP3 W 0 2 EP2 W 0 1 EP1 W 0 0x20 0 EP0 W 0 MICROFRAME contains a count 0-7 that indicates which of the 125 microsecond microframes last occurred. This register is active only when SX2 is operating in high speed mode (480 Mbits/sec). 9.13 FNADDR Register 0x2D During the USB enumeration process, the host sends a device a unique 7-bit address that the SX2 copies into this register. There is normally no reason for the external master to know its USB device address because the SX2 automatically responds only to its assigned address. FNADDR Bit # Bit Name Read/Write Default 7 HSGRANT R 0 6 FA6 R 0 5 FA5 R 0 4 FA4 R 0 3 FA3 R 0 2 FA2 R 0 1 FA1 R 0 0x2D 0 FA0 R 0 FIFO8 FIFO6 FIFO4 FIFO2 W 0 W 0 W 0 W 0 Bit [4..7]: FIFOx These bits allows the external master to selectively flush any or all of the endpoint FIFOs. By writing the desired endpoint FIFO bit, SX2 logic flushes the selected FIFO. For example setting bit 7 flushes endpoint 8 FIFO. Bit [3..0]: EPx These bits are is used only for IN transfers. By writing the desired endpoint number (2,4,6 or 8), SX2 logic automatically commits an IN buffer to the USB host. For example, for committing a packet through endpoint 6, set the lower nibble to 6: set bits 1 and 2 high. Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high speed. Set to 0 if the SX2 enumerated at full speed. Bit[6..0]: Address set by the host. Document #: 38-08013 Rev. *J Page 22 of 45 [+] Feedback CY7C68001 9.14 INTENABLE Register 0x2E This register is used to enable/disable the various interrupt sources, and by default all interrupts are enabled. INTENABLE Bit # Bit Name Read/Write Default 7 6 5 4 1 3 1 2 1 SETUP EP0 FLAGS BUF R/W 1 R/W 1 R/W 1 0x2E 0 ENUM BUS READY OK ACTIVITY R/W 1 R/W 1 R/W 1 9.14.6 READY Bit 0 Setting this bit to a 1 enables an interrupt when the SX2 has powered on and performed an internal self-test. 9.15 DESC Register 0x30 This register address is used to write the 500-byte descriptor RAM. The external master writes two bytes (four command data transfers) to this address corresponding to the length of the descriptor or VID/PID/DID data to be written. The external master then consecutively writes that number of bytes into the descriptor RAM in nibble format. For complete details, refer to Enumeration on page 8. R/W R/W 1 1 9.14.1 SETUP Bit 7 Setting this bit to a 1 enables an interrupt when a setup packet is received from the USB host. 9.14.2 EP0BUF Bit 6 Setting this bit to a 1 enables an interrupt when the Endpoint 0 buffer becomes available. 9.14.3 FLAGS Bit 5 Setting this bit to a 1 enables an interrupt when an OUT endpoint FIFO's state transitions from empty to not-empty. 9.14.4 ENUMOK Bit 2 Setting this bit to a 1 enables an interrupt when SX2 enumeration is complete. 9.14.5 BUSACTIVITY Bit 1 Setting this bit to a 1 enables an interrupt when the SX2 detects an absence or presence of bus activity. 9.16 EP0BUF Register 0x31 This register address is used to access the 64-byte Endpoint 0 buffer. The external master can read or write to this register to complete Endpoint 0 data transfers. For complete details, refer to Endpoint 0 on page 8. 9.17 SETUP Register 0x32 This register address is used to access the 8-byte setup packet received from the USB host. If the external master writes to this register, it can stall Endpoint 0. For complete details, refer to Endpoint 0 on page 8. 9.18 EP0BC Register 0x33 This register address is used to access the byte count of Endpoint 0. For Endpoint 0 OUT transfers, the external master can read this register to get the number of bytes transferred from the USB host. For Endpoint 0 IN transfers, the external master writes the number of bytes in the Endpoint 0 buffer to transfer the bytes to the USB host. For complete details, refer to Endpoint 0 on page 8. Document #: 38-08013 Rev. *J Page 23 of 45 [+] Feedback CY7C68001 10. Absolute Maximum Ratings Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Supplied...... 0C to +70C Supply Voltage to Ground Potential................-0.5V to +4.0V DC Input Voltage to Any Pin ........................................ 5.25V DC Voltage Applied to Outputs in High-Z State ........................ -0.5V to VCC + 0.5V Power Dissipation.................................................... 936 mW Static Discharge Voltage.......................................... > 2000V 11. Operating Conditions TA (Ambient Temperature Under Bias) ............. 0C to +70C Supply Voltage................................................+3.0V to +3.6V Ground Voltage.................................................................. 0V FOSC (Oscillator or Crystal Frequency) ..................... 24 MHz 100-ppm Parallel Resonant 12. DC Electrical Characteristics Table 12-1. DC Characteristics Parameter VCC VIH VIL II VOH VOL IOH IOL CIN ISUSP ISUSP ICC TRESET Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Voltage High Output Voltage Low Output Current High Output Current Low Input Pin Capacitance Suspend Current Suspend Current Supply Current RESET Time after valid power Except D+/D- D+/D- Includes 1.5k integrated pull up Excluding 1.5k integrated pull up Connected to USB at high speed Connected to USB at full speed VCC min = 3.0V 1.91 250 30 200 90 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 400 180 260 150 Conditions[12] Min 3.0 2 -0.5 Typ 3.3 Max 3.6 5.25 0.8 10 Unit V V V A V V mA mA pF pF A A mA mA mS 13. AC Electrical Characteristics 13.1 USB Transceiver USB 2.0-certified compliant in full and high speed. Note 12. Specific conditions for ICC measurements: HS typical 3.3V, 25C, 48 MHz; FS typical 3.3V, 25C, 48 MHz. Document #: 38-08013 Rev. *J Page 24 of 45 [+] Feedback CY7C68001 13.2 Command Interface Figure 13-1. Command Synchronous Read Timing Diagram[13] tIFCLK IFCLK tSRD SLRD tRDH tINT INT# DATA tOEon SLOE N tOEoff Table 13-1. Command Synchronous Read Parameters with Internally Sourced IFCLK Parameter tIFCLK tSRD tRDH tOEon tOEoff tINT IFCLK period SLRD to Clock Setup Time Clock to SLRD Hold Time SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold Clock to INT# Output Propagation Delay Description Min 20.83 18.7 0 10.5 10.5 9.5 Max Unit ns ns ns ns ns ns Table 13-2. Command Synchronous Read with Externally Sourced IFCLK[14] Parameter tIFCLK tSRD tRDH tOEon tOEoff tINT IFCLK Period SLRD to Clock Setup Time Clock to SLRD Hold Time SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold Clock to INT# Output Propagation Delay Description Min 20 12.7 3.7 10.5 10.5 13.5 Max 200 Unit ns ns ns ns ns ns Notes 13. Dashed lines denote signals with programmable polarity. 14. Externally sourced IFCLK must not exceed 50 MHz. Document #: 38-08013 Rev. *J Page 25 of 45 [+] Feedback CY7C68001 Figure 13-2. Command Synchronous Write Timing Diagram[13] tIFCLK IFCLK SLWR tSWR tSFD tWRH tFDH DATA N tNRDY tNRDY READY Table 13-3. Command Synchronous Write Parameters with Internally Sourced IFCLK Parameter tIFCLK tSWR tWRH tSFD tFDH tNRDY IFCLK Period SLWR to Clock Setup Time Clock to SLWR Hold Time Command Data to Clock Setup Time Clock to Command Data Hold Time Clock to READY Output Propagation Time Description Min 20.83 18.1 0 9.2 0 9.5 Max Unit ns ns ns ns ns ns Table 13-4. Command Synchronous Write Parameters with Externally Sourced IFCLK[14] Parameter tIFCLK tSWR tWRH tSFD tFDH tNRDY IFCLK Period SLWR to Clock Setup Time Clock to SLWR Hold Time Command Data to Clock Setup Time Clock to Command Data Hold Time Clock to READY Output Propagation Time Description Min 20 12.1 3.6 3.2 4.5 13.5 Max 200 Unit ns ns ns ns ns ns Figure 13-3. Command Asynchronous Read Timing Diagram[13] tRDpwh SLRD tRDpwl tXINT INT# tIRD DATA tOEon SLOE N tOEoff Document #: 38-08013 Rev. *J Page 26 of 45 [+] Feedback CY7C68001 Table 13-5. Command Read Parameters Parameter tRDpwl tRDpwh tIRD tXINT tOEon tOEoff Description SLRD Pulse Width LOW SLRD Pulse Width HIGH INTERRUPT to SLRD SLRD to INTERRUPT SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold tWRpwh Min 50 50 0 Max Unit ns ns ns 70 10.5 10.5 ns ns ns Figure 13-4. Command Asynchronous Write Timing Diagram[13] tWRpwl SLWR tSFD DATA tRDYWR READY tRDY tFDH Table 13-6. Command Write Parameters Parameter tWRpwl tWRpwh tSFD tFDH tRDYWR tRDY SLWR Pulse LOW SLWR Pulse HIGH SLWR to Command DATA Setup Time Command DATA to SLWR Hold Time READY to SLWR Time SLWR to READY Description Min 50 70 10 10 0 70 Max Unit ns ns ns ns ns ns 13.1 FIFO Interface Figure 13-5. Slave FIFO Synchronous Read Timing Diagram[13] tIFCLK IFCLK tSRD SLRD tRDH tXFLG FLAGS DATA tOEon SLOE N N+1 tXFD tOEoff Document #: 38-08013 Rev. *J Page 27 of 45 [+] Feedback CY7C68001 Table 13-7. Slave FIFO Synchronous Read with Internally Sourced IFCLK[14] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Setup Time Clock to SLRD Hold Time SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Description Min 20.83 18.7 0 10.5 10.5 9.5 11 Max Unit ns ns ns ns ns ns ns Table 13-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK[14] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Setup Time Clock to SLRD Hold Time SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Figure 13-6. Slave FIFO Synchronous Write Timing tIFCLK IFCLK Description Min 20 12.7 3.7 Max 200 Unit ns ns ns 10.5 10.5 13.5 15 Diagram[13] ns ns ns ns SLWR tSWR tWRH DATA tSFD FLAGS N tFDH tXFLG Table 13-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[14] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK Period SLWR to Clock Setup Time Clock to SLWR Hold Time FIFO Data to Clock Setup Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Description Min 20.83 18.1 0 9.2 0 9.5 Max Unit ns ns ns ns ns ns Document #: 38-08013 Rev. *J Page 28 of 45 [+] Feedback CY7C68001 Table 13-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[14] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK Period SLWR to Clock Setup Time Clock to SLWR Hold Time FIFO Data to Clock Setup Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Description Min 20 12.1 3.6 3.2 4.5 13.5 Max Unit ns ns ns ns ns ns Figure 13-7. Slave FIFO Synchronous Packet End Strobe Timing Diagram[13] IFCLK tPEH PKTEND tSPE FLAGS tXFLG Table 13-11. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK[14] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Setup Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min 20.83 14.6 0 9.5 Max Unit ns ns ns ns Table 13-12. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK[14] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Setup Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min 20 8.6 2.5 13.5 Max 200 Unit ns ns ns ns There is no specific timing requirement that needs to be met for asserting PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is the setup time tSPE and the hold time tPEH must be met. Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. There is an additional timing requirement that need to be met when the FIFO is configured to operate in auto mode and it is desired to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this particular scenario, user must make sure to assert PKTEND at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. Document #: 38-08013 Rev. *J Page 29 of 45 [+] Feedback CY7C68001 Figure 13-8. Slave FIFO Synchronous Write Sequence and Timing Diagram tIFCLK IFCLK tSFA tFAH FIFOADR >= tSWR >= tWRH SLWR tSFD tFDH tSFD X-3 tFDH tSFD X-2 tFDH tSFD X-1 tFDH tSFD X tFDH tSFD 1 tFDH DATA X-4 At least one IFCLK cycle tSPE tPEH PKTEND Figure 13-8. shows a scenario where two packets are being committed. The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, results in the FX2 failing to send the one byte/word short packet. Figure 13-9. Slave FIFO Synchronous Address Timing Diagram IFCLK SLCS#/FIFOADR[2:0] tSFA tFAH Table 13-13. Slave FIFO Synchronous Address Parameters[14] Parameter tIFCLK tSFA tFAH Description Interface Clock Period FIFOADR[2:0] to Clock Setup Time Clock to FIFOADR[2:0] Hold Time Min 20 25 10 Max 200 Unit ns ns ns Document #: 38-08013 Rev. *J Page 30 of 45 [+] Feedback CY7C68001 Figure 13-10. Slave FIFO Asynchronous Read Timing Diagram[13] tRDpwh SLRD tRDpwl tXFLG FLAGS tXFD DATA SLOE N tOEon N+1 tOEoff Table 13-14. Slave FIFO Asynchronous Read Parameters[15] Parameter tRDpwl tRDpwh tXFLG tXFD tOEon tOEoff Description SLRD Pulse Width Low SLRD Pulse Width HIGH SLRD to FLAGS Output Propagation Delay SLRD to FIFO Data Output Propagation Delay SLOE Turn on to FIFO Data Valid SLOE Turn off to FIFO Data Hold Min 50 50 70 15 10.5 10.5 Max Unit ns ns ns ns ns ns Figure 13-11. Slave FIFO Asynchronous Write Timing Diagram[13] tWRpwh SLWR/SLCS# tWRpwl tSFD DATA tXFD tFDH FLAGS Table 13-15. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[15] Parameter tWRpwl tWRpwh tSFD tFDH tXFD SLWR Pulse LOW SLWR Pulse HIGH SLWR to FIFO DATA Setup Time FIFO DATA to SLWR Hold Time SLWR to FLAGS Output Propagation Delay Description Min 50 70 10 10 70 Max Unit ns ns ns ns ns Document #: 38-08013 Rev. *J Page 31 of 45 [+] Feedback CY7C68001 Figure 13-12. Slave FIFO Asynchronous Packet End Strobe Timing Diagram tPEpwh PKTEND tPEpwl FLAGS tXFLG Table 13-16. Slave FIFO Asynchronous Packet End Strobe Parameters[15] Parameter tPEpwl tPWpwh tXFLG Description PKTEND Pulse Width LOW PKTEND Pulse Width HIGH PKTEND to FLAGS Output Propagation Delay Min 50 50 110 Max Unit ns ns ns Figure 13-13. Slave FIFO Asynchronous Address Timing Diagram[13] SLCS/FIFOADR[2:0] tSFA SLRD/SLWR/PKTEND tFAH Table 13-17. Slave FIFO Asynchronous Address Parameters[15] Parameter tSFA tFAH tFAH Description FIFOADR[2:0] to RD/WR/PKTEND Setup Time SLRD/PKTEND to FIFOADR[2:0] Hold Time SLWR to FIFOADR[2:0] Hold Time Min 10 20 70 Max Unit ns ns ns 13.1 Slave FIFO Address to Flags/Data Following timing is applicable to synchronous and asynchronous interfaces. Figure 13-14. Slave FIFO Address to Flags/Data Timing Diagram[12] FIFOADR [2.0] tXFLG FLAGS tXFD DATA N N+1 Table 13-18. Slave FIFO Address to Flags/Data Parameters Parameter tXFLG tXFD Description FIFOADR[2:0] to FLAGS Output Propagation Delay FIFOADR[2:0] to FIFODATA Output Propagation Delay Min Max 10.7 14.3 Unit ns ns Note 15. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz. Document #: 38-08013 Rev. *J Page 32 of 45 [+] Feedback CY7C68001 13.1 Slave FIFO Output Enable Following timings are applicable to synchronous and asynchronous interfaces. Figure 13-15. Slave FIFO Output Enable Timing Diagram[12] SLOE tOEoff DATA tOEon Table 13-19. Slave FIFO Output Enable Parameters Parameter tOEon tOEoff Description SLOE assert to FIFO DATA Output SLOE deassert to FIFO DATA Hold Min Max 10.5 10.5 Unit ns ns 13.1 Sequence Diagram Figure 13-16. Slave FIFO Synchronous Read Sequence and Timing Diagram tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSRD tRDH T=0 >= tSRD >= tRDH SLRD t=2 t=3 T=2 T=3 SLCS tXFLG FLAGS tXFD tXFD N+1 tOEoff tOEon N+1 N+2 tXFD N+3 tXFD N+4 tOEoff DATA Data Driven: N tOEon SLOE t=1 t=4 T=1 T=4 Figure 13-17. Slave FIFO Synchronous Sequence of Events Diagram IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK FIFO POINTER N SLOE N SLRD N+1 SLOE SLRD N+1 SLOE N+1 SLRD N+2 N+2 N+3 N+3 N+4 SLRD N+4 SLOE N+4 Not Driven FIFO DATA BUS Not Driven Driven: N N+1 Not Driven N+1 N+4 N+4 Document #: 38-08013 Rev. *J Page 33 of 45 [+] Feedback CY7C68001 Figure 13-16. shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. If the SLCS signal is used, it must be asserted with SLRD, or before SLRD is asserted (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. At = 1, SLOE is asserted. SLOE is an output enable only, whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example it is the first data value in the FIFO. Note: the data is pre-fetched and is driven on the bus when SLOE is asserted. At t = 2, SLRD is asserted. SLRD must meet the setup time of tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the deassertion of the SLRD signal). The FIFO pointer is updated on the rising edge of the IFCLK, while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value read from the FIFO. In order to have data on the FIFO data bus, SLOE MUST also be asserted. The same sequence of events are shown for a burst read and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. Figure 13-18. Slave FIFO Synchronous Write Sequence and Timing Diagram[13] tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSWR tWRH T=0 >= tSWR >= tWRH SLWR t=2 t=3 T=2 T=5 SLCS tXFLG tXFLG FLAGS tSFD tFDH N t=1 T=1 tSFD N+1 tFDH tSFD N+2 tFDH tSFD N+3 T=4 tFDH DATA T=3 tSPE tPEH PKTEND Document #: 38-08013 Rev. *J Page 34 of 45 [+] Feedback CY7C68001 Figure 13-18. shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin. data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. As shown in Figure 13-19. once the four bytes are written to the FIFO, SLWR is deasserted. The short 4-byte packet can be committed to the host by asserting the PKTEND signal. There is no specific timing requirement that needs to be met for asserting PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only consideration is the setup time tSPE and the hold time tPEH must be met. In the scenario of Figure 13-19., the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND can be asserted in subsequent clock cycles. The FIFOADDR lines should be held constant during the PKTEND assertion. Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exists when the FIFO is configured to operate in auto mode and it is desired to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this case, the external master must make sure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications) Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. At t = 1, the external master/peripheral must output the data value onto the data bus with a minimum set up time of tSFD before the rising edge of IFCLK. At t = 2, SLWR is asserted. The SLWR must meet the setup time of tSWR (time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of tWRH (time from the IFCLK edge to the de-assertion of the SLWR signal). If SLCS signal is used, it must be asserted with SLWR or before SLWR is asserted. (that is, the SLCS and SLWR signals must both be asserted to start a valid write condition). * While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag is also updated after a delay of tXFLG from the rising edge of the clock. The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, after the SLWR is asserted, the data on the FIFO Figure 13-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh SLRD t=2 t=3 T=2 T=3 T=4 T=5 T=6 SLCS tXFLG tXFLG FLAGS tXFD tXFD N tOEoff tOEon N+1 tXFD N+2 tXFD N+3 tOEoff DATA Data (X) Driven tOEon N SLOE t=1 t=4 T=1 T=7 Document #: 38-08013 Rev. *J Page 35 of 45 [+] Feedback CY7C68001 Figure 13-20. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE FIFO POINTER N N Driven: X N N N+1 N+1 Not Driven N+1 N N+1 N+1 N+2 N+1 N+2 N+2 N+3 N+2 N+3 Not Driven FIFO DATA BUS Not Driven N Figure 13-20. diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. At t = 0 the FIFO address is stable and the SLCS signal is asserted. At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data, it data that was in the FIFO from a prior read cycle. At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of tRDpwl and minimum de-active pulse width of tRDpwh. If SLCS is used then, SLCS must be asserted with SLRD or before SLRD is asserted (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 13-21., data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (that is, SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together. The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note: In burst read mode, during SLOE is assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. Figure 13-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram[13] tSFA tFAH tSFA tFAH FIFOADR t=0 tWRpwl tWRpwh T=0 tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh SLWR t =1 t=3 T=1 T=3 T=4 T=6 T=7 T=9 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH N+1 T=2 T=5 tSFD tFDH N+2 tSFD tFDH N+3 T=8 DATA t=2 N tPEpwl tPEpwh PKTEND Figure 13-21. diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented. In Figure 13-21. once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. Page 36 of 45 At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted. At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR. At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer. Document #: 38-08013 Rev. *J [+] Feedback CY7C68001 14. Default Descriptor //Device Descriptor 18, //Descriptor length 1, //Descriptor type 00,02, //Specification Version (BCD) 00, //Device class 00, //Device sub-class 00, //Device sub-sub-class 64, //Maximum packet size LSB(VID),MSB(VID),//Vendor ID LSB(PID),MSB(PID),//Product ID LSB(DID),MSB(DID),//Device ID 1, //Manufacturer string index 2, //Product string index 0, //Serial number string index 1, //Number of configurations //DeviceQualDscr 10, //Descriptor length 6, //Descriptor type 0x00,0x02, //Specification Version (BCD) 00, //Device class 00, //Device sub-class 00, //Device sub-sub-class 64, //Maximum packet size 1, //Number of configurations 0, //Reserved //HighSpeedConfigDscr 9, //Descriptor length 2, //Descriptor type 46, //Total Length (LSB) 0, //Total Length (MSB) 1, //Number of interfaces 1, //Configuration number 0, //Configuration string 0xA0, //Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) 50, //Power requirement (div 2 ma) //Interface Descriptor 9, //Descriptor length 4, //Descriptor type 0, //Zero-based index of this interface 0, //Alternate setting 4, //Number of end points 0xFF, //Interface class 0x00, //Interface sub class 0x00, //Interface sub sub class 0, //Interface descriptor string index //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x02, //Endpoint number, and direction 2, //Endpoint type 0x00, //Maximum packet size (LSB) 0x02, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type Document #: 38-08013 Rev. *J Page 37 of 45 [+] Feedback CY7C68001 0x04, 2, 0x00, 0x02, 0x00, //Endpoint number, and direction //Endpoint type //Maximum packet size (LSB) //Max packet size (MSB) //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x86, //Endpoint number, and direction 2, //Endpoint type 0x00, //Maximum packet size (LSB) 0x02, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x88, //Endpoint number, and direction 2, //Endpoint type 0x00, //Maximum packet size (LSB) 0x02, //Max packet size (MSB) 0x00, //Polling interval //FullSpeedConfigDscr 9, //Descriptor length 2, //Descriptor type 46, //Total Length (LSB) 0, //Total Length (MSB) 1, //Number of interfaces 1, //Configuration number 0, //Configuration string 0xA0, //Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) 50, //Power requirement (div 2 ma) //Interface Descriptor 9, //Descriptor length 4, //Descriptor type 0, //Zero-based index of this interface 0, //Alternate setting 4, //Number of end points 0xFF, //Interface class 0x00, //Interface sub class 0x00, //Interface sub sub class 0, //Interface descriptor string index //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x02, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x04, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval Document #: 38-08013 Rev. *J Page 38 of 45 [+] Feedback CY7C68001 //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x86, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type 0x88, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval //StringDscr //StringDscr0 4, 3, 0x09,0x04, //StringDscr1 16, 3, 'C',00, 'y',00, 'p',00, 'r',00, 'e',00, 's',00, 's',00, //StringDscr2 20, 3, 'C',00, 'Y',00, '7',00, 'C',00, '6',00, '8',00, '0',00, '0',00, '1',00, //String descriptor length //String Descriptor //US LANGID Code //String descriptor length //String Descriptor //String descriptor length //String Descriptor Document #: 38-08013 Rev. *J Page 39 of 45 [+] Feedback CY7C68001 15. General PCB Layout Guidelines[16] The following recommendations should be followed to ensure reliable high-performance operation. 16. Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the SX2 through the device's metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame(R) (MLF(R)) Packages." This application note can be downloaded from Amkor's web site from the following URL: http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 16-1. on page 40 displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that "No Clean" type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Figure 16-2. is a plot of the solder mask pattern and Figure 16-3. displays an X-Ray image of the assembly (darker areas indicate solder). At least a four-layer impedance controlled boards are required to maintain signal quality. Specify impedance targets (ask your board vendor what they can achieve). To control impedance, maintain trace widths and trace spacing. Minimize stubs to minimize reflected signals. Connections between the USB connector shell and signal ground must be done near the USB connector. Bypass/flyback caps on VBus, near connector, are recommended. DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm. Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. It is preferred to have no vias placed on the DPLUS or DMINUS trace routing. Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. Figure 16-1. Cross section of the Area Underneath the QFN Package 0.017" dia Solder Mask Cu Fill Cu Fill PCB Material 0.013" dia PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. Figure 16-2. Plot of the Solder Mask (White Area) Figure 16-3. X-Ray Image of the Assembly Note 16. Source for recommendations: High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf. Document #: 38-08013 Rev. *J Page 40 of 45 [+] Feedback CY7C68001 17. Ordering Information Ordering Code CY7C68001-56PVC CY7C68001-56LFC CY7C68001-56PVXC CY7C68001-56LFXC CY3682 CY7C68001-56LTXC 56 SSOP 56 QFN 56 SSOP, Pb-free 56 QFN, Pb-free EZ-USB SX2 Development Kit 56 QFN, Pb-free Package Type 18. Package Diagrams Figure 18-1. 56-Pin Shrunk Small Outline Package 056 51-85062-*C Document #: 38-08013 Rev. *J Page 41 of 45 [+] Feedback CY7C68001 Figure 18-2. 56-Pin QFN (8X8 mm) 51-85144 *G Figure 18-3. 56-Pin Sawn QFN (8X8X1.00 mm) 51-85187 *D Document #: 38-08013 Rev. *J Page 42 of 45 [+] Feedback CY7C68001 19. Document History Page Description Title: CY7C68001 EZ-USB SX2TM High Speed USB Interface Device Document Number: 38-08013 REV. ** *A ECN No. 111807 123155 Submission Date 06/07/02 02/07/03 Origin of Change BHA BHA New Data Sheet Minor clean-up and clarification Removed references to IRQ Register and replaced them with references to Interrupt Status Byte Modified pin-out description for XTALIN and XTALOUT Added CS# timing to Figure , Figure , and Figure 13-13. Changed Command Protocol example to IFCONFIG (0x01) Edited PCB Layout Recommendations Added AR#10691 Added USB high speed logo Default state of registers specified in section where the register bits are defined Reorganized timing diagram presentation: First all timing related to synchronous interface, followed by timing related to asynchronous interface, followed by timing diagrams common to both interfaces Provided further information in section 5.3 regarding boot methods Provided timing diagram that encapsulates ALL relevant signals for a synchronous and asynchronous slave read and write interface Added section on (QFN) Package Design Notes FIFOADR[2:0] Hold Time (tFAH) for Asynchronous FIFO Interface has been updated as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns; SLWR to FIFOADR[2:0] Hold Time:70 ns (recommended) Added information on the polarity of the programmable flag Fixed the Command Synchronous Write Timing Diagram Fixed the Command Asynchronous Write Timing Diagram Added information on the delay required when endpoint configuration registers are changed after SX2 has already enumerated Added Test ID for the USB Compliance Test Added information on the fact that the SX2 does not automatically respond to Set/Clear Feature Endpoint (Stall) request, external master intervention required Added information on accessing undocumented register which are not indexed (for resetting data toggle) Added information on requirement of clock stability before releasing reset Added information on configuration of PF register for full speed Updated confirmed timing on FIFOADR[2:0] Hold Time (tFAH)for Asynchronous FIFO Interface has been updated Corrected the default bit settings of EPxxFLAGS register Added information on how to change SLWR/SLRD/SLOE polarities Added further information on buffering interrupt on initiation of a command read request Change the default state of the FNADDR to 0x00 Added further labels on the sequence diagram for synchronous and asynchronous read and write in single and burst mode Added information on the maximum delay allowed between each descriptor byte write once a command write request to register 0x30 has been initiated by the external master Description of Change *B 126324 07/02/03 MON *C 129463 10/07/03 MON Document #: 38-08013 Rev. *J Page 43 of 45 [+] Feedback CY7C68001 Description Title: CY7C68001 EZ-USB SX2TM High Speed USB Interface Device Document Number: 38-08013 *D 130447 12/17/03 KKU Replaced package diagram in Figure 18-2. spec number 51-85144 with clear image Fixed last history entry for rev *C Change reference in section 2.7.2.4 from XXXXXXX to 7.3 Removed the word "compatible" in section 3.3 Change the text in section 5.0, last paragraph from 0xE6FB to 0xE683 Changed label "Reset" to "Default" in sections 5.1 and 7.2 through 7.14 Reformatted Figure 4 Added entries 3A, 3B, 3C, 0xE609, and 0xE683 to Figure 9-1 Change access on hex values 07 and 09 from bbbbbbbb to bbbbrbrr Removed tXFD from Figure 13-9. and Figure 13-10. and tables 11-1,2, and 5 Corrected timing diagrams, figures 11-1,11-2, 11-6 Changed Figure 13-16. through Figure 13-21. for clarity, text which followed had reference to t3 which should be t2, added reference of t3 for deasserting SLWR and reworded section 11.6 Updated ICC typical and maximum values Reformatted data sheet to latest format Added Lead-free parts numbers Updated default value for address 0x07 and 0x09 Added Footnote 3. Removed requirement of less then 360 nsec period between nibble writes in command Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max value of 70 ns to 110 ns Provided additional timing restrictions and requirement regarding the use of PKTEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode) Miscellaneous grammar corrections. Added 3.4.3 section header. Fixed command sequence step 3 to say register value instead of High Byte of Register Address (upper and lower nibble in two places). Removed statement that programmable flag polarity is set to active low and cannot be altered. Programmable flag relies on DECIS bit settings. Updated Amkor application note URL. Changed TXINT in Figure 11-3 to be from deassertion edge of SLRD. Changed TRDY in Figure 11-4 to be from deassertion edge of SLWR. Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty and from not-empty to empty conditions for triggering this interrupt. Modified Figure 5-1. to fit across columns. It was getting cropped in half. Changed corporate address to 198 Champion Court. Added information in section USB Signaling Speed on page 2 on Full Speed only enumeration. *E 243316 See ECN KKU *F 329238 See ECN KEV *G *H *I *J 392570 411515 2665531 2733374 See ECN See ECN 02/26/2009 07/08/2009 KEV BHA DPT/PYRS Added package diagram (51-85187) and updated Ordering Information table. Updated template ANTG/AESA Updated cross-references on pages 2 and 3 Updated section numbers Document #: 38-08013 Rev. *J Page 44 of 45 [+] Feedback CY7C68001 20. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2002-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. PSoC DesignerTM is a trademark and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-08013 Rev. *J Revised July 07, 2009 Page 45 of 45 [+] Feedback |
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